An Ultra Low-Power ADc for Wireless Micro-sensor Applications

Autonomous micro-sensor nodes rely on low-power circuits to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work pursues the design of an ultra low-power analog-to-digital converter (ADC) whose sampling rate and resolution can be scaled to dynamically recover power savings. The proposed ADC has a sampling rate of 0-100 kS/s and a resolution of either 12 or 8 bits. The design is based on the successive approximation register architecture (SAR), which is suitable for scaleable, micro-power operation. Specifically, the number of active blocks has been minimized to allow efficient power-gating, which, inturn, has been leveraged to implement scalability features. Several new techniques to improve the efficiency of the ADC have been developed and employed. Analog offset calibration in the regenerative latch is used, to improve the power-delay product of the comparator; pre-amplifier cascade optimization is performed with consideration to thermal noise limitations; weak-inversion biasing is employed in the active amplifiers; passive switch-capacitors are used to generate the auto-zero reference voltage such the CMRR of the ADC is maximized; integrated capacitors are laid-out in a new common-centroid arrangement that minimizes edge effects; finally, the sub-DAC's transmission gain is adjusted to reduce non-linearities caused by the attenuating effects of parasitics. The ADC has been fabricated in a 0.18pLm CMOS technology. All circuits are powered using a IV supply, though bootstrapping is used internally. At a resolution of 12-bits, and a sampling rate of 100 kS/s, the power consumption of the entire ADC core is 26pW. The SNDR of the converter with a 48 kHz input tone is 65dB (10.55 ENOB) and the SFDR is 71dB. The power consumption decreases linearly with sampling rate, and is measured to be approximately 200nW at 500 S/s. Thesis Supervisor: Anantha P. Chandrakasan Title: Professor of Electrical Engineering